Processing devices, such as central processing units (CPUs), often implement one or more timers to control operations to provide periodic stimuli during normal operations or to facilitate the measurement of certain performance characteristics. However, interruptions to normal program flow due to exceptions often can negatively affect correct timer operation. For instance, when a conventional CPU enters an interrupt handling routine to handle an exception, the timers of the CPU typically continue to operate unless explicitly disabled after entering the handler by performing writes to control registers associated with the timers. Likewise, when the CPU exits the interrupt handling routine, the timers disabled for the interrupt handling routine typically are reenabled by performing writes to the control registers associated with the timers. However, the number of clock cycles needed to perform these write operations may vary due to a variety of factors and thus may introduce a non-deterministic error into the timer values. This non-deterministic error factor can make it difficult to adequately characterize certain process profiling characteristics under test. Further, the write operations themselves consume processing cycles, thereby reducing overall processing efficiency. Accordingly, an improved technique for controlling timers in response to exceptions in a processing device would be advantageous.